This repository contains a custom implementation of a pipelined CPU based on the RISC-V RV32IMC instruction set architecture. The design leverages pipelining to achieve higher instruction throughput and efficient hardware utilization.
- RV32IMC Support: Implements the full 32-bit base integer instruction set (RV32I), plus multiplication and division extensions (M), and compressed instruction extension (C).
- 5-Stage Pipeline: Fetch, Decode, Execute, Memory, and Write-back stages for efficient instruction processing.
- Hazard Handling: Includes basic mechanisms for data forwarding and pipeline stalling to resolve data and control hazards.
- Memory Interface: Supports interaction with instruction and data memory modules.
- Testbench: Reference testbench for simulation and validation.
├── rtl
├── docs
├── assembly-tests
├── README.md
├── LICENSE
- Verilog/SystemVerilog simulator (e.g., Icarus Verilog, ModelSim, or Vivado)
- RISC-V toolchain for generating machine code
- Clone the repository:
git clone https://github.com/vlsienthusiast00x/rv32imc-pipelined-cpu.git cd rv32imc-pipelined-cpu - Compile the source code
cd rtl make all - Run the simulation and inspect the waveform/logs for correct behavior.
vvp rv32imc.vvp
- Change the code in
instr.Sfile for testing different operations
Click Here for some sample test assembly codes
- rtl/: Contains the main CPU pipeline design, ALU, register file, control logic, and memory interface.
- docs/: Includes architecture diagrams, pipeline stage explanations, and performance analysis.
- assembly-tests/: Provides some sample ready-to-compile assembly codes, that completely proves each instruction of this CPU.
See the docs folder for:
- Pipeline architecture overview
- Block/Architectural diagram
- Hazard detection and forwarding logic
- Example instruction flows
- RISC-V GNU toolchain installation
Feel free to open issues, suggest improvements, or submit pull requests for bug fixes and enhancements.
This project is licensed under the MIT License.
Created by vlsienthusiast00x