Synchronous RAM module in SystemVerilog — Implements an 8-bit wide, 128-location Random Access Memory with read and write enable controls, clocked operation, active high reset and parameterized addressing. Suitable for FPGA/ASIC design projects, memory initialization, and digital system simulations.
This project implements a synchronous ROM and RAM in SystemVerilog, featuring an 8-bit data width and 128 addressable locations. It supports clocked operation with separate read and write enable controls, using parameterized addressing for scalability.
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