Virtual Satellite 4 - FDIR Application
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Updated
Dec 15, 2022 - Java
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fault-modeling
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VLSI test project: 4-bit ripple carry adder with random stuck-at fault injection. Supports ATPG-based verification, fault modeling, and simulation for learning and experimentation
testing simulation verilog hdl vlsi icarus atpg fault-modeling vlsi-testing stuck-at-faults vlsi-verification
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Updated
Sep 23, 2025 - Python
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