SAFARI Research Group at ETH Zurich and Carnegie Mellon University
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115 repositories
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)
RawBench
PublicMQSim
PublicMQSim is a fast & accurate simulator for modern multi-queue (MQ) and SATA SSDs. MQSim faithfully models new high-bandwidth protocol implementations, steady-state SSD conditions, and full end-to-end latency of requests in modern SSDs. Described in detail in the FAST 2018 paper: http://usenix.org/system/files/conference/fast18/fast18-tavakkol.pdf- RawHash can accurately and efficiently map raw nanopore signals to reference genomes of varying sizes (e.g., from viral to a human genomes) in real-time without basecalling. Described by Firtina et al. (published at https://academic.oup.com/bioinformatics/article/39/Supplement_1/i297/7210440).
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
- EasyDRAM is an FPGA-based framework for rapid and accurate end-to-end evaluation of DRAM techniques on real DRAM chips. Described in our DSN 2025 paper: https://arxiv.org/abs/2506.10441
- Data and code for the VTS'25 paper "Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies." Described in our VTS 2025 paper: https://www.arxiv.org/pdf/2503.16749
Virtuoso
PublicVirtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation methodology for estimating OS overheads and models diverse VM designs, incorporating state-of-the-art TLB techniques, page table structures etc. More details in our ASPLOS 2025 paper: https://arxiv.org/pdf/2403.04635PIM-TC
PublicPIM-TC implements a distributed Triangle Counting (TC) algorithm specifically designed for and evaluated on the UPMEM Processing-in-Memory (PIM) architecture. Described in our paper https://arxiv.org/abs/2505.04269.PyGim
PublicPyGim is the first runtime framework to efficiently execute Graph Neural Networks (GNNs) on real Processing-in-Memory systems. It provides a high-level Python interface, currently integrated with PyTorch, and supports various GNN models and real-world input graphs. Described by SIGMETRICS'25 by Giannoula et al. (https://arxiv.org/pdf/2402.16731)- IMPACT is a new framework that leverages Processing-in-Memory (PiM) to amplify data leakage in main memory-based timing attacks. More details: https://arxiv.org/abs/2404.11284
PIMDAL
PublicPIMDAL (PIM Data Analytics Library) is an implementation of DB operators and 5 TPC-H queries on the UPMEM PIM system. Additionally we provide code to generate the TPC-H data and reference implementations on the CPU and GPU. Described in our arxiv paper: https://arxiv.org/abs/2504.01948- A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
PaCRAM
PublicPaCRAM is a technique that reduces the performance and energy overheads of the existing RowHammer mitigation mechanisms by carefully reducing the latency of preventive refreshes issued by existing mitigation mechanisms without compromising system security. Described in the HPCA 2025 paper: https://arxiv.org/abs/2502.11745Ariadne
PublicAriadne is a new compressed swap scheme for mobile devices that reduces application relaunch latency and CPU usage while increasing the number of live applications for enhanced user experience. Described in the HPCA 2025 paper by Liang et al.: https://arxiv.org/pdf/2502.12826MIMDRAM
PublicSource code for the architectural simulator used for modeling the PUD system proposed in our HPCA 2024 paper `MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing''. Paper is at: https://arxiv.org/pdf/2402.19080.pdf- PIM-ML is a benchmark for training machine learning algorithms on the UPMEM architecture, which is the first publicly-available real-world processing-in-memory (PIM) architecture. Described in the ISPASS 2023 paper by Gomez-Luna et al. (https://arxiv.org/pdf/2207.07886.pdf).
- MegIS is the first in-storage processing system designed to significantly reduce the data movement overhead of the end-to-end metagenomic analysis pipeline. Described in the ISCA 2024 paper by Mansouri Ghiasi et al.: https://arxiv.org/pdf/2406.19113
BreakHammer
PublicBreakHammer is a technique that reduces the performance overhead of RowHammer mitigation mechanisms by carefully reducing the number of performed RowHammer-preventive actions without compromising system robustness. Described in the MICRO 2024 paper: https://arxiv.org/abs/2404.13477.PIM-Opt
PublicSource code & scripts for distributed machine learning training workloads on a real-world Processing-In-Memory system (i.e., UPMEM). Described in our PACT'24 paper by Rhyner et al. at https://arxiv.org/pdf/2404.07164v2Genome-on-Diet
PublicGenome-on-Diet is a fast and memory-frugal framework for exemplifying sparsified genomics for read mapping, containment search, and metagenomic profiling. It is much faster & more memory-efficient than minimap2 for Illumina, HiFi, and ONT reads. Described by Alser et al. (preliminary version: https://arxiv.org/abs/2211.08157).Sectored-DRAM
PublicA new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (ii) activating a disproportionately large number of DRAM cells at low cost. Described in our paper https://arxiv.org/pdf/2207.13795.rawasm
PublicLoad-Inspector
PublicA binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arxiv.org/pdf/2406.18786AirLift
PublicAirLift is a tool that updates mapped reads from one reference genome to another. Unlike existing tools, It accounts for regions not shared between the two reference genomes and enables remapping across all parts of the references. Described by Kim et al. (preliminary version at http://arxiv.org/abs/1912.08735)SiMRA-DRAM
PublicSource code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input majority operations and 3) copying one row's content to up 31 rows in real DDR4 DRAM chips. Described in our DSN'24 paper by Yuksel et al. at https://arxiv.org/abs/2405.06081HBM-Read-Disturbance
PublicDetailed read disturbance (RowHammer and RowPress) characterization of six real HBM2 DRAM chips yielding 23 new observations and 8 new takeaways, as described in the DSN'24 paper https://arxiv.org/pdf/2310.14665.pdf