EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques
DSN 2025

EasyDRAM is an open-source infrastructure that enables fast and accurate end-to-end evaluation of DRAM techniques on FPGAs. This repository contains the full source code for EasyDRAM, including hardware modules, simulation infrastructure, and benchmarks.

An extended version of our conference paper is available at https://arxiv.org/abs/2506.10441.

Repository Structure

• prebuilt
  Contains a ready-made EasyDRAM system bitstream. To generate this bitstream or bitstreams for other designs, see Section "Generating an EasyDRAM Bitstream".

• easydram-chipyard/
  A modified version of Chipyard that includes EasyDRAM integration.

  • generators/easydram/
    This directory contains the main RTL implementation of EasyDRAM.

• easydram-ramulator/
  Contains our Ramulator-based evaluation infrastructure for DRAM techniques.
  This version includes our evaluation of RowClone within Ramulator 2.0.
  Our PolyBench traces and SolarDRAM implementation will be released soon.

• easydram-programs/
  A collection of benchmarks and programs used for testing and evaluating EasyDRAM.
  For example:

  • tests/easymemory/simload_basic/ contains a simple program that initializes the software memory controller on simulated workload processors and performs a copy from a source array to a destination array using EasyDRAM.

Generating an EasyDRAM Bitstream

If you prefer to generate your own bitstream from source, we provide instructions below. If not, you may use the prebuilt bitstream prebuilt/EasyDRAM.bit.

EasyDRAM builds on the Chipyard framework. A bitstream for the AMD/Xilinx VCU108 board can be generated in 2 steps:

1. cd easydram-chipyard/fpga/
2. make SUB_PROJECT=vcu108easyboom

Please see the relevant chapter in Chipyard documentation for more details.

Reproducing the Results in the Paper

We provide a send_benchmark.sh script to easily run an experiment using EasyDRAM.

Executing the following command runs the trisolv workload from Polybench in an EasyDRAM system programmed with the basic FRFC-FS memory controller design in the FPGA board.

./send_benchmark.sh /dev/ttyUSB0 frfcfs_mc trisolv EasyDRAMRocketConfig

Detailed instructions on using the script is provided here.

Citation

If you use this infrastructure in your work, please cite our DSN 2025 paper:

@inproceedings{canpolat2025easydram,
  title     = {{EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques}},
  author    = {Canpolat, Oğuzhan and Olgun, Ataberk and Novo, David and Ergin, Oğuz and Mutlu, Onur},
  booktitle = {DSN},
  year      = {2025}
}

Contacts

Oğuzhan Canpolat (aqwoguz [at] gmail [dot] com)
Ataberk Olgun (ataberk [dot] olgun [at] safari [dot] ethz [dot] ch)