Restore DSim support for CV32E40P simulations #2608
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MikeOpenHWGroup
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DO NOT MERGE
Common Infrastructure
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I see many references to cv32e40p_tb_wrapper that probably need to be changed to cv32e40p_core_tb_wrapper. I listed them below:
cv32e40p/sim/tools/dsim/ccov_scopes.txt
cv32e40p/sim/tools/vcs/vcs.tcl
cv32e40p/tb/core/cv32e40p_core_tb_wrapper.sv
cv32e40p/tb/uvmt/uvmt_cv32e40p_dut_wrap.sv
cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv
cv32e40p/tb/uvmt/uvmt_cv32e40p_macros.sv
cv32e40p/tb/uvmt/uvmt_cv32e40p_step_compare.sv
cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv
In any case, I can confirm that the basic hello world core and UVM tests can run on DSIM locally for me.
| bit select_fp_instr, include_fpc, rand_status; | ||
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| rand_status = std::randomize(select_fp_instr) with {select_fp_instr dist {0:=1, 1:=1};}; | ||
| assert(rand_status) else begin `uvm_error(_header, $sformatf("assertion error")); end |
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Do you know if the removal of the else ... assertion error is just because they are not informative, or they actually had a purpose before? :)
| // SPDX-License-Identifier: Apache-2.0 WITH SHL-0.51 | ||
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| module cv32e40p_tb_wrapper | ||
| module cv32e40p_core_tb_wrapper |
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The comment on line 13 also needs to be changed from cv32e40p_tb_wrapper to cv32e40p_core_tb_wrapper, and cv32e40p_wrapper module to cv32e40p_core module
| task uvme_cv32e40p_reduced_rand_debug_req_c::rand_delay(); | ||
| if (!std::randomize(dly) with {dly inside {[2500:10000]};}) begin | ||
| `uvm_fatal("RAND_DEBUG_RAND_DELAY", "Randomization dly Failed") | ||
| if (! std::randomize(dly) with { dly inside {[1:10000]}; } ) begin |
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Do you know why this delay was not randomized from 1 since before? I don't think it is relevant to the PR, I am just curious.
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DSim was not used for CV32E40P v2 and so there was some bit-rot within both the scriptware and testbench. Also, there is a known bug with DSim which means it cannot handle macros with concatenated parameters. This PR include a kludge to comment-out the offending code.