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@miczyg1 miczyg1 commented Aug 17, 2024

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@krystian-hebel krystian-hebel deleted the branch aem-4.17.4 August 26, 2024 11:41
@SergiiDmytruk SergiiDmytruk reopened this Aug 30, 2024
@SergiiDmytruk SergiiDmytruk changed the base branch from aem-4.17.4 to aem-phase4-rebase August 30, 2024 22:01
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I think this PR got closed accidentally due to target branch removed, so I changed its base (didn't rebase the branch) and reopened.

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miczyg1 commented Sep 5, 2024

I think this PR got closed accidentally due to target branch removed, so I changed its base (didn't rebase the branch) and reopened.

I can see Krystian deleted the branch and it made a mess from this PR... Anyway, it was not yet solving the problem I had.

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I can see Krystian deleted the branch and it made a mess from this PR... Anyway, it was not yet solving the problem I had.

The mess is the result of me changing the target branch to be able to reopen the PR. Rebasing the top 2 commits will fix this, I just didn't want to fix the PR without fixing your local branch.

@miczyg1 miczyg1 force-pushed the aem_boot_delay_fix branch 3 times, most recently from ca95ec5 to e91a466 Compare September 15, 2024 13:07
Map the TPM event log after the TXT regions are mapped to avoid
an early page fault when booting with slaunch.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Right now the MTRRs were restored in an ugly way, while MTRR enable bit
was set and caching was not disabled. Mimic the generic Xen MTRR driver
behavior when changing MTRRs.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The MTRR capabilities and default type were read before the MTRRs were
restored in slaunch flow. The restoration itself updated the MTRR default
type MSR, so the mtrr_top_of_ram had invalid state in mtrr_cap and
mtrr_def variables. Move reading those MSRs after MTRRs are restored
in slaunch flow.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Do the check if IA32_FEATURE_CONTROL has the proper bits enabled to run
VMX in SMX when slaunch is active.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
…ities

The bootloader should prepare the MTRR masks using MAXPHYADDRs. On modern
Intel platforms, the SINIT ACM forces this bit to be 1 according to
TXT MLE Software Development Guide Revision 017.4.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Report the SMX and TXT capabilitiesso that dom0 can query the
Intel TXT support information using xl dmesg.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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3 participants