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Update BitBltArmSimdSourceWord.s to latest ben avison version #592

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Update BitBltArmSimdSourceWord.s to latest ben avison version #592

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2e07c41
Update BitBltArmSimdSourceWord.s to latest ben avison version
timrowledge Sep 6, 2021
5c87395
Update mvm files for ARMv8 assert and debug squeak.cog.spur builds
timrowledge Sep 6, 2021
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2 changes: 2 additions & 0 deletions building/linux64ARMv8/squeak.cog.spur/build.assert/mvm
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@ set -e
# assert Cog Spur VM with VM profiler and threaded heartbeat
INSTALLDIR=assert/sqcogspur64ARMv8linuxht
# armv8.N-a all fail in signalSemaphoreWithIndex for N in 1,2,3,4,5
# tpr - add enablementisation of fast bitblt ben avison code
MACHINE="-march=armv8-a -mtune=cortex-a72"
OPT="-g3 -O1 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -DDEBUGVM=0"

Expand All @@ -21,6 +22,7 @@ test -f plugins.ext || (test -f ../plugins.ext && cp -p ../plugins.ext . || cp -
test -f config.h || ../../../../platforms/unix/config/configure \
--with-vmversion=5.0 --with-src=src/spur64.cog \
--without-vm-display-fbdev --without-npsqueak \
--enable-fast-bitblt \
CFLAGS="$MACHINE $OPT -DCOGMTVM=0 -DDUAL_MAPPED_CODE_ZONE=1" \
LIBS="-lrt"

Expand Down
2 changes: 2 additions & 0 deletions building/linux64ARMv8/squeak.cog.spur/build.debug/mvm
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Expand Up @@ -3,6 +3,7 @@ set -e
# debug Cog Spur VM with VM profiler and threaded heartbeat
INSTALLDIR=debug/sqcogspur64ARMv8linuxht
# armv8.N-a all fail in signalSemaphoreWithIndex for N in 1,2,3,4,5
# tpr - add enablementisation of fast bitblt ben avison code
MACHINE="-march=armv8-a -mtune=cortex-a72"
OPT="-g3 -O0 -DDEBUGVM=1 -DAIO_DEBUG=1"

Expand All @@ -21,6 +22,7 @@ test -f plugins.ext || (test -f ../plugins.ext && cp -p ../plugins.ext . || cp -
test -f config.h || ../../../../platforms/unix/config/configure \
--with-vmversion=5.0 --with-src=src/spur64.cog \
--without-vm-display-fbdev --without-npsqueak \
--enable-fast-bitblt \
CFLAGS="$MACHINE $OPT -DCOGMTVM=0 -DDUAL_MAPPED_CODE_ZONE=1" \
LIBS="-lrt"

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19 changes: 12 additions & 7 deletions platforms/Cross/plugins/BitBltPlugin/BitBltArmSimdSourceWord.s
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Original file line number Diff line number Diff line change
Expand Up @@ -528,7 +528,7 @@ counter SETA counter + 4

SourceWord GenerateFunctions 1, 4,, \
FLAG_COLOUR_MAP :OR: FLAG_DST_WRITEONLY :OR: FLAG_SPILL_LINE_VARS :OR: FLAG_NO_EXPAND_SKEW, 2, \
"stride_s,map,bitptrs,orig_w,scratch", \
"stride_s,map,bitptrs,scratch,orig_w", \
"x,stride_s,bitptrs", orig_w,, init ; leading_pixels_reg=wk3

; ********************************************************************
Expand Down Expand Up @@ -951,16 +951,16 @@ counter SETA counter + 4

MACRO
SourceWord1_2_128bits_head $src, $fixed_skew, $intra_preloads
Read2Words src, 3, carry, $fixed_skew, skew, $wk0
Read2Words src, 2, carry, $fixed_skew, skew, $wk0
MEND

MACRO
SourceWord1_2_128bits_tail $src
LCLA counter
counter SETA 0
WHILE counter < 16
MSR CPSR_f, $wk3
MOV $wk3, $wk3, LSL #4
MSR CPSR_f, $wk2
MOV $wk2, $wk2, LSL #4
ORRPL $wk0, ht, $wk0, LSL #2
ORRMI $wk0, ht_info, $wk0, LSL #2
ORRNE $wk0, ht, $wk0, LSL #2
Expand All @@ -973,8 +973,8 @@ counter SETA counter + 4
WEND
counter SETA 0
WHILE counter < 16
MSR CPSR_f, $wk3
MOV $wk3, $wk3, LSL #4
MSR CPSR_f, $wk2
MOV $wk2, $wk2, LSL #4
ORRPL $wk1, ht, $wk1, LSL #2
ORRMI $wk1, ht_info, $wk1, LSL #2
ORRNE $wk1, ht, $wk1, LSL #2
Expand All @@ -987,8 +987,13 @@ counter SETA counter + 4
WEND
counter SETA 0
WHILE counter < 16
[ counter = 0
MSR CPSR_f, $wk3
MOV $wk4, $wk3, LSL #4
|
MSR CPSR_f, $wk4
MOV $wk4, $wk4, LSL #4
]
ORRPL $wk2, ht, $wk2, LSL #2
ORRMI $wk2, ht_info, $wk2, LSL #2
ORRNE $wk2, ht, $wk2, LSL #2
Expand Down Expand Up @@ -5661,4 +5666,4 @@ SourceWord GenerateFunctions 0, 32, _scalar, \

; ********************************************************************

END
END