UART 16550 Verilog Implementation

A synthesizable Verilog implementation of the classic UART 16550 serial interface, featuring configurable baud rate, FIFO buffering, parity, and error detection.

Features ✨

• Configurable Baud Rate: Set via programmable divisor latches.
• FIFO Buffers: 16-byte transmit and receive FIFOs for efficient data handling.
• Parity Support: Even, odd, sticky, or no parity.
• Word Length Selection: 5, 6, 7, or 8 data bits per frame.
• Stop Bit Selection: 1 or 2 stop bits.
• Break Control: Ability to send break signals.
• Error Detection: Parity, framing, and overrun error flags.
• Register Interface: Implements UART 16550 registers (LCR, FCR, LSR, SCR).
• Testbenches: Provided for all major modules.

Architecture 🏗️

The UART core consists of several main blocks:

• Register Block (uart_regs.v): Handles configuration, status, and control registers, including baud rate generation.
• Transmit FIFO (fifo_top.v): Buffers outgoing data before transmission.
• Receive FIFO (fifo_top.v): Buffers incoming data after reception.
• Transmitter (uart_tx_top.v): Serializes parallel data, adds start/stop/parity bits, and drives the TX line.
• Receiver (uart_rx_top.v): Samples the RX line, reconstructs parallel data, checks parity and framing, and detects errors.
• Top-Level Integration (uart_top.v): Connects all blocks, manages data flow, and exposes the UART interface.

Data written to the UART is stored in the transmit FIFO, then serialized and sent out. Incoming serial data is deserialized, checked for errors, and stored in the receive FIFO. All configuration and status is managed via the register block.

Missing Features / Limitations ⚠️

• Modem Control & Status: No implementation of modem control/status registers (MCR/MSR).
• Interrupts: No interrupt generation or handling logic.
• DMA Support: DMA mode is not implemented.
• Multi-UART Support: Only a single UART instance per module.

File Structure 📁

• uart_top.v — Top-level UART module integrating all submodules.
• uart_tx_top.v — UART transmitter logic.
• uart_rx_top.v — UART receiver logic.
• fifo_top.v — FIFO buffer implementation.
• uart_regs.v — UART register set and control logic.
• *_tb.v — Testbenches for each module.

Simulation & Testing 🧪

• Each module includes a dedicated testbench (*_tb.v) demonstrating typical usage.
• Run testbenches to verify functionality before hardware integration.

License 📄

This project is licensed under the MIT License.